1. Field of the Invention
The present invention generally relates to a data transmission system, in particular, to an apparatus for resolving conflicts happened between two I2C slave devices with the same addressed address.
2. Description of Related Art
An inter-integrated circuit (I2C) bus is a conventional industrial standard serial bus and applied to a current computer system, for serving as a connection and a data transmission medium between a plurality of integrated circuits or chips of the computer system. Generally, when a plurality of I2C integrated circuits or I2C chips intends to perform the data transmission by using an I2C bus, one of the plurality of I2C integrated circuits or I2C chips must be an I2C master device, for example, a south bridge chip, and the rest are I2C slave devices of the I2C master device.
Accordingly, only the addressed I2C slave devices may perform the data transmission with the I2C master device through the I2C bus. It is well-known that the I2C bus usually includes one serial data (SDA) signal line and one serial clock (SCL) signal line, in which the SDA signal line is usually used to transmit signals such as starting, address, data, controlling, ensuring, and stopping, and the SCL signal line is used to transmit a clock. It should be understood that the technique is known by those skilled in the art, and is not repeated here.
Here, it should be noted that a disadvantage of the data transmission performed by using the I2C bus in the conventional art is that when the plurality of I2C slave devices has the same addressed address, that is, at least two I2C slave devices are addressed at the same time, the I2C master device cannot accurately perform the data transmission with the I2C slave devices with the same addressed address.
In order to effectively resolve the problem, in the conventional art, it is proposed that the time, when the I2C slave devices with the same addressed address are addressed by the I2C master device, is separated by using a buffer, and thus only one addressed I2C slave device exists at a time, so as to resolve the disadvantage resulting from the data transmission by using the I2C bus in the conventional art. However, a resulted disadvantage is that the cost for design is increased.
In addition, it should be further noted that some I2C slave devices must be addressed by the I2C master device only before a basic input/output system (BIOS) completes a power-on self-test (POST), so as to perform the data transmission subsequently, but all the I2C slave devices are not addressed by the I2C master device after the BIOS completes the POST. Therefore, the I2C master device cannot perform the data transmission with all the I2C slave devices on real time.